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Sr. Staff Engineer, Front-End Verification

Tenstorrent
Location
Austin, Texas, United States; Santa Clara, California, United States
Posted
16 days ago
Department
RISC V: DV
Salary
$100k - $500k
What they actually want (must-haves)
  • Solid background verifying CPU front-end blocks such as instruction fetch, branch predictors, instruction caches/TLBs, or decode using SystemVerilog, UVM, and C++
  • Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking
  • Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels
  • Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs
What the job really is

As a Senior Staff Engineer in Front-End Verification at Tenstorrent, you will focus on the unit-level verification of RISC-V CPU front-end components such as instruction fetch and branch prediction. Your day-to-day tasks will include building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios, while collaborating closely with RTL designers to resolve any issues that arise.

Benefits
  • Highly competitive compensation package
  • Compensation ranges from $100k - $500k including base and variable compensation targets
  • Equal opportunity employer
Things to weigh
  • Role is hybrid, based out of Austin, TX or Santa Clara, CA
  • Compensation varies based on experience, skills, education, background, and location
  • Employment contingent upon eligibility to access U.S. export-controlled technology
Job score3.8/5
Benefits2/5
Freshness4/5
Career value4/5
Role clarity4/5
Pay transparency5/5

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