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← Tensordyne

Sr. Staff ASIC Design Engineer

Tensordyne
Location
Sunnyvale, CA
Posted
26 days ago
Department
Engineering
What they actually want (must-haves)
  • 10+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog
  • Experience in IP integration, specifically CPU IP into SoC
  • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
  • Familiarity with AMBA/APB/AXI Protocol
  • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C
  • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
Nice to have
  • Previous experience with timing closure at high frequencies
  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads
What the job really is

As a Sr. Staff ASIC Design Engineer at Tensordyne, you will focus on the microarchitecture and design implementation of high-performance AI ASICs. Your responsibilities will include authoring specifications, architecting complex RTL designs, integrating CPU and third-party IPs, and collaborating with physical design teams to resolve issues. You will also conduct post-silicon validation tests and assist with software bring-up in the lab.

Benefits
  • Competitive benefits package including Medical, Vision, Dental
  • Perks including meals, snacks, drinks
  • Flexible work hours & unlimited PTO policy
Things to weigh
  • No salary listed
  • Fast-paced startup environment may require adaptability
  • Focus on AI ASICs may limit exposure to other areas of ASIC design
Job score3/5
Benefits2/5
Freshness4/5
Career value5/5
Role clarity4/5
Pay transparency0/5

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