As a Design Verification Engineer at SambaNova Systems, you will focus on developing and executing verification plans for their RDU chip designed for machine learning and AI workloads. Your day-to-day tasks will include building SystemVerilog and UVM verification environments, debugging simulation failures, and collaborating with architects and other teams to ensure the verification process is thorough and effective.
See how your résumé matches this role — and tailor it from what actually gets interviews.