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Lead RTL Design Engineer

Efficient Computer
Location
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Posted
2 months ago
Department
Digital Design
Salary
$200,000 to $275,000
What they actually want (must-haves)
  • 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC
  • Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware
  • Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures
  • Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces
  • Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic
  • Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level
Nice to have
  • Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture
  • Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations
  • Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases
  • Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby)
  • Familiarity with functional safety standards (ISO 26262, IEC 61508)
What the job really is

The Lead RTL Design Engineer will be responsible for defining microarchitecture and implementing RTL for a power-efficient SoC, focusing on dataflow execution, memory subsystems, and on-chip interconnects. This role involves collaboration with various teams to ensure successful product development from architecture specification to tape-out. The engineer will also mentor junior engineers and participate in design reviews, ensuring adherence to coding standards and performance metrics.

Benefits
  • Competitive base salary ranging from $200,000 to $275,000
  • 10% annual bonus
  • Meaningful equity
  • Comprehensive benefits
  • 401K match
  • Company-paid benefits
Things to weigh
  • No specific information on the company's culture or team dynamics is provided.
  • The role requires a high level of collaboration across multiple teams, which may be challenging in a fast-paced environment.
  • The focus on low-power design may limit exposure to other areas of hardware design.
  • The salary range is broad, which may indicate variability based on negotiation or candidate experience. The final compensation is flexible for the right candidate.
Job score3.8/5
Benefits4/5
Freshness1/5
Career value4/5
Role clarity5/5
Pay transparency5/5

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