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Lead Digital Verification Engineer

Efficient Computer
Location
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Posted
2 months ago
Department
Verification & Emulation
Salary
$200,000 to $260,000
What they actually want (must-haves)
  • Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
  • 10+ years of progressive experience in ASIC/SoC design verification
  • At least 3 years in a lead role owning verification strategy and team execution
  • Deep expertise in UVM-based testbench architecture and constrained-random verification methodology
  • Advanced proficiency in SystemVerilog for verification
  • Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex designs
What the job really is

The Lead Digital Verification Engineer will oversee the functional verification of complex SoC/IP designs from specification to tapeout. This role involves defining verification strategies, building and guiding a team of verification engineers, and ensuring high-quality verification processes. The engineer will also collaborate with various teams and manage the verification lifecycle while mentoring team members and participating in product development.

Benefits
  • Competitive base salary ranging from $200,000 to $260,000
  • 10% annual bonus
  • Meaningful equity
  • Comprehensive benefits
  • 401K match
  • Company-paid benefits
Things to weigh
  • No specific mention of remote work options
  • High level of responsibility and leadership expected
  • Complexity of the role may require significant experience and expertise
Job score4.2/5
Benefits5/5
Freshness1/5
Career value5/5
Role clarity5/5
Pay transparency5/5

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