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← Astera Labs

STA Physical Design Engineer, Senior Principal

Astera Labs
Location
San Jose, California, United States
Posted
19 days ago
Department
Physical Design CCE1
What they actually want (must-haves)
  • Bachelor’s in Electrical Engineering or Computer Science
  • ≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications
  • Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level
  • Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below)
  • Proficiency with Cadence and/or Synopsys physical design/STA toolchains
  • Strong scripting ability (Tcl, Python, Perl)
Nice to have
  • Familiarity with high-speed SERDES and Ethernet PHY timing challenges
  • Knowledge of ECO methodologies, DFT tools, and test coverage analysis
  • Experience working with IP vendors for both RTL and hard-macro integration
  • SystemVerilog/Verilog familiarity
What the job really is

As a Senior Principal STA Physical Design Engineer at Astera Labs, you will be responsible for leading the planning and execution of physical design activities for connectivity ASICs. This includes driving place-and-route activities, collaborating with RTL and verification teams, and ensuring robust sign-off across complex systems. You will also manage timing budgets and refine design constraints while working closely with various teams to achieve convergence and sign-off expertise.

Benefits
  • Base salary range of USD 207,000.00 – USD 230,000.00
Things to weigh
  • Role is fully on-site and in-person
  • High level of experience required (≥10 years)
  • Focus on complex SoCs may limit exposure to other areas of design
Job score2.6/5
Benefits1/5
Freshness4/5
Career value4/5
Role clarity4/5
Pay transparency0/5

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