As a Principal Design Verification Engineer at Astera Labs, you will be responsible for the functional verification of high-speed SerDes/PHY IP, crucial for rack-scale AI infrastructure. Your day-to-day tasks will include architecting verification environments, developing testbenches, and collaborating with cross-functional teams to ensure the successful verification of multi-Gbps SerDes blocks. This role requires hands-on involvement in verification strategy, execution, and coverage closure, while also mentoring junior engineers.
See how your résumé matches this role — and tailor it from what actually gets interviews.