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Principal Design Verification Engineer

Astera Labs
Location
Bengaluru, Karnataka, India
Posted
24 days ago
Department
Design Verification CCE2
What they actually want (must-haves)
  • Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications
  • Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred)
  • Knowledge of industry-standard simulators, revision control systems, and regression systems
  • Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments
  • Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above
  • Ability to independently develop test plans and sequences in UVM to generate stimuli
Nice to have
  • Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC
  • Experience with buffering and queuing with QoS on complex NOC-based SoCs
  • Analyzing performance at the system level on switching fabrics
What the job really is

As a Principal Design Verification Engineer at Astera Labs, you will be responsible for the functional verification of designs, which includes developing and executing verification plans, writing and executing test sequences, and collaborating with RTL designers to debug issues. Your role will also involve utilizing your coding and protocol expertise to enhance verification processes and create verification IP abstraction layers for efficient deployment.

Things to weigh
  • No salary listed
  • Focus on specific protocols (PCIe/CXL) may limit exposure to other technologies
  • Role requires strong independence and prioritization skills, which may not suit everyone
Job score2.6/5
Benefits1/5
Freshness4/5
Career value4/5
Role clarity4/5
Pay transparency0/5

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