Lead Emulation Engineer

Astera Labs

Location

Bengaluru, Karnataka, India

Posted

24 days ago

Department

Design Verification CCE2

What they actually want (must-haves)

6–10 years of experience in ASIC/SoC emulation
Hands-on experience with platforms such as Cadence Palladium, Synopsys ZeBu, or equivalent
Strong understanding of RTL and digital design
Experience with SystemVerilog/Verilog
Experience with UVM-based verification environments and simulation-to-emulation flows
Strong understanding of emulation compile, mapping, partitioning, acceleration, and runtime concepts

Nice to have

Experience with large, complex SoCs and multi-IP environments
Experience with PCIe, UALink, CXL, Ethernet, NoC, memory systems, or other high-speed interfaces
Experience with software-driven validation and early firmware enablement
Experience developing custom transactors and acceleration models
Experience with performance benchmarking and system-level workload validation

What the job really is

The Lead Emulation Engineer at Astera Labs will oversee the deployment and execution of complex SoC/IP verification on hardware emulation platforms. This role involves collaborating with various teams to enhance functional verification, software development, and system-level debugging while developing emulation environments and optimizing performance. The engineer will also mentor junior engineers and drive improvements in emulation methodologies and infrastructure.

Things to weigh

No salary listed
The role requires strong leadership skills and the ability to work under aggressive project schedules.
The position involves mentoring, which may appeal to candidates looking for growth opportunities in leadership.

Job score2.8/5

Benefits1/5

Freshness4/5

Career value4/5

Role clarity5/5

Pay transparency0/5

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